Full performance utilization of an electronic circuit technology requires circuit operation at the highest possible operating frequency. An increase in the operating frequency of a logic circuit translates to a decrease in both the data and clock periods and thus a decrease in the width of the data and clock pulses.
Pulse distortion is defined as the shrinkage or expansion of pulse width and amplitude as electronic signals (pulses) propagate through circuits; it is always present independent of the operating frequency or technology used. As the operating frequency increases to accommodate higher performance requirements, pulse distortion becomes noticeable because the distortion becomes a significant percentage of the pulse width. As the operating frequency increases still further, the effect of pulse distortion becomes so severe that the pulse width and amplitude shrink to a point where erroneous data is clocked. Finally, at still higher frequencies pulse propagation ceases altogether.
To achieve high-speed performance in an electronic circuit design, the highest reliable operating frequency must be determined. The pulse distortion characteristics of the logic and the delay through the circuits govern this frequency. According to the prior art, one technique for determining the highest reliable operating frequency as a function of pulse distortion involves simply implementing the minimum pulse width specifications for the particular technology (e.g., CMOS, Bipolar) in which the design is to be constructed. These specifications, which are made available by circuit fabrication vendors, represent conservative generalized guidelines which limit pulse width to a specific minimum value in order to guarantee correct propagation for all possible conditions and any design using the technology. These specifications are directed to "correct by construction" standard logic block or gate array design systems for implementing VLSI circuits quickly and easily, but sacrifice circuit performance and density to ensure that designs are fail-safe. Such guidelines limit the operating frequency well below the technology limit.
Another prior art technique, which deals more directly with maximizing performance by determining pulse distortion characteristics for a circuit design, is to subject the design to rigorous simulation using one of the numerous commercially available analog circuit simulation tools running on a digital computer. This approach provides the most accurate method for calculating pulse distortion, but suffers the drawback of being very computation intensive. Thus the computation time required to analyze a logic block or a complete VLSI chip according to this approach is prohibitive.
A third prior art technique for dealing with pulse distortion centers around determining the arrival time of "edges" (transitions between high and low logical signal values) in an electronic circuit by way of statistical calculations performed on a digital computer. A general problem with this approach is that it characterizes pulse distortion in terms of pulse width only, as opposed to both pulse width and amplitude. More particularly, the calculations, which are based on timing analysis theory, lead to inaccurate pulse width characterizations, because the latest leading edge and the earliest trailing edge are chosen to define the pulse width. In fact, these edges are not logically related, and do not form a logic "pulse." Finally, this approach relies on data that focuses on best and worst case delay times, rather than on pulse width distortion. Best/worst case delay data can yield unjustifiably optimistic pulse width distortion estimates.
In summary, the prior art methods for determining pulse distortion are inadequate when applied to logic blocks or whole VLSI circuit designs, either because their computation cost is prohibitive, or because they are able to characterize pulse distortion in terms of pulse width only and produce results which are not accurate enough to be useful.